Quiz 1.1: Systems Architecture
Which architecture allows instructions and data to share the same memory in the fetch-decode-execute cycle?
Which CPU component stores instructions and data currently in use?
Which of the following is considered an input device?
In the Von Neumann architecture, what does the fetch-decode-execute cycle enable?
What is the clock speed of an 8GHz CPU with four-cores?
How many instructions per second can a 4GHz octacore CPU process?
Which register holds the memory address of the instruction about to be used?
How is CPU clock speed measured?
Which of the following statements about embedded systems is true?
Which component is responsible for keeping track of the memory address of the next instruction to be fetched?